VLSI KOREA NETWORK
VLSI ResearchSEMICONDUCTOR KNOWLEDGE GRAPH
PREVIEW · PRIMARY SOURCE REQUIRED

Chiplet interconnect design-space exploration

Paper · Journal record preview · 2025 preview

Author record ESystems architecture lab
STRUCTURED ABSTRACT

A structured route from paper assumptions to a reproducible model, standard requirements and product context.

Key metrics

Latency · source pendingSOURCE STATE ATTACHED
Link energy · source pendingSOURCE STATE ATTACHED
Topology · source pendingSOURCE STATE ATTACHED

Reproduction state

이 미리보기 레코드는 재현 성공을 주장하지 않습니다. 운영 레코드는 코드, pinned revision, tool versions, commands, logs와 결과 artifact를 구분해 표시합니다.

RELATED CALENDAR

Conference & CFP

Dates stay authoritative in VLSI Calendar.

Open Calendar →